`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 11/24/2019 12:46:50 PM
// Design Name: 
// Module Name: clock_cyx
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module clock_generate(
    input wire clk100mhz,
    output reg clk5hz
    );
    
    
    parameter freq = 5;
    
    integer i;
    
    initial
    begin
        i = 0;
        clk5hz = 0;
    end
    
    always @ (posedge clk100mhz)
    begin
        i <= i + 1;
        if (i == 50000000 / freq)
        begin
            i <= 0;
            clk5hz <= ~clk5hz;
        end
    end
endmodule




module clock_cyx(
    input wire clk100m,
    //input wire clk_ext,
    input wire clear,
    input wire buzz_state,
    input wire clk_ext,
    input wire work_state,
    input wire set_but,
    output wire[3:0] EN,
    output wire[7:0] digi,
    output wire buzzer,
    output wire CO_hrs
    );
    
    parameter clock_freq = 20;
    
    reg  buzzer_working;
    wire buzzer_freq, CO_min;
    wire[3:0] digi3, digi2, digi1, digi0;
    wire[5:0] min_cnt, hrs_cnt;
    wire clk_min;
    wire set_but_stab;
    
    assign clk_min = work_state ? set_but_stab : clk_ext;
    
    //assign ext_led = clk_ext;
    
    button_stablizer my_stab(
        .clk100m(clk100m),
        .but(set_but),
        .but_stab(set_but_stab)
    );
    
    counter_test 
        #(.MAX(60))
    min_counter_cyx_60(
        //out
        .CNT(min_cnt),
        .CO(CO_min),
        //in
        .RST(clear),
        .CLK(clk_min)
    );
    
    counter_test
        #(.MAX(24))
    hrs_counter_cyx_60(
        //out
        .CNT(hrs_cnt),
        .CO(CO_hrs),
        //in
        .RST(clear),
        .CLK(CO_min)
    );
    
    
    assign digi3 = hrs_cnt / 10;
    assign digi2 = hrs_cnt % 10;
    assign digi1 = min_cnt / 10;
    assign digi0 = min_cnt % 10;
    
    always @ (min_cnt)
    begin
        if (min_cnt >= 54)
            buzzer_working = 1;
        else buzzer_working = 0;
    end
    
    Digits_dynamic_display_0 cyx_counter_display(
        //out
        .EN3(EN[3]),
        .EN2(EN[2]),
        .EN1(EN[1]),
        .EN0(EN[0]),
        .a(digi[7]),
        .b(digi[6]),
        .c(digi[5]),
        .d(digi[4]),
        .e(digi[3]),
        .f(digi[2]),
        .g(digi[1]),
        .dp(digi[0]),
        //in
        .AN3(digi3),
        .AN2(digi2),
        .AN1(digi1),
        .AN0(digi0),
        .clk100(clk100m)
    );
    /*
    clock_generate
        #(.freq(clock_freq))
    my_clock(
        .clk100mhz(clk100m),
        .clk5hz(clk_ext)
    );
    */
    clock_generate
        #(.freq(800))
    my_buzzer(
        .clk100mhz(clk100m),
        .clk5hz(buzzer_freq)
    );
    
    assign buzzer = buzzer_working & buzzer_freq & buzz_state;
    
endmodule
